1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more particularly, to a system for universal spatial pattern recognition of data formats on semiconductor wafers.
2. Description of the Related Art
Semiconductor wafer fabrication involves complex manufacturing processes to produce integrated circuits on the surface of silicon wafers. In order to characterize the quality of a wafer, each die is associated with a wafer test bin containing an alphanumeric code that represents the type of functional and non-functional die. The collective wafer test bins are grouped to generate a bin summary or a wafer map showing the locations of faulty dice and the type of manufacturing faults associated with these dice.
A goal of semiconductor manufacturing is to attain a high yield rate from all wafers during the device lifetime. Generally, random fault patterns do not provide information on the manufacturing process that can be used to enhance the yield. Conversely, uniform or non-random fault patterns serve as a guide to provide valuable feedback to a fab for identifying the sources of faults. However, large volumes of wafers are manufactured wherein each wafer contains its own bin summary. Management of the large volumes of bin summaries is critical to identifying manufacturing faults and providing effective modifications of the manufacturing process.
Conventional fault tracking methods rely on an “eyeball” technique in which an experienced semiconductor process engineer manually examines selected sample wafers and makes his best judgment as to the cause of the faults. This “eyeball” technique is limited because the analysis is done only on selected sample wafers. This manual technique is labor intensive and time consuming. Moreover, it does not provide data storage for correlating with future test data.
Throughout the semiconductor manufacturing process, a significant amount of information is collected and related to wafers in a positional or coordinate format. These data formats lend themselves to being analyzed spatially, as well as numerically, due to the additional information provided by the coordinate data. Recognizing the pattern significance along with the other numeric references is extremely important in solving yield problems rapidly.
Accordingly, it is desirable to produce a method for automating the wafer test bin in processing of manufacturing faults on semiconductor wafers to generate a representative wafer map showing meaningful fault patterns to maximize the effectiveness of a spatial analysis system wherein all types of patterns associated numeric outputs are evaluated in or by a common platform.